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THC63LVD103D _rev.3.0_e copyright?2011 thine electronics, inc. 1/12 thine electronics, inc. THC63LVD103D 160mhz 30bits colo r lvds transmitter general description the THC63LVD103D transmitter is designed to sup- port pixel data transmission between host and flat panel display from ntsc up to 1080p(60hz). the THC63LVD103D converts 35bits of cmos/ttl data into lvds(low voltag e differential signaling) data stream. the transmitter can be programmed for ris- ing edge or falling edge clocks through a dedicated pin. at a transmit clock frequency of 160mhz, 30bits of rgb data and 5bits of timing and control data (hsync, vsync, de, cntl1, cntl2) are transmit- ted at an effective rate of 1.12gbps per lvds channel. features ? wide dot clock range: 8-160mhz suited for ntsc, vga, svga, xga,sxga and sxga+ and 1080p ? pll requires no external components ? supports spread spectrum clock generator ? on chip jitter filtering ? clock edge selectable ? supports reduced swing lvds for low emi ? power down mode ? low power single 3.3v cmos design ? 64pin tqfp ? pin compatible with thc63lvd103(30bits) block diagram parallel to serial ta +/- tb +/- tc +/- td +/- te +/- ta0-6 7 cmos/ttl input lvds output rs clk in (8 to160mhz) td0-6 7 tb0-6 pll tc0-6 tclk +/- (8 to 160mhz) 7 7 7 te0-6 7 r/f /pdwn 7
copyright?2011 thine electronics, inc. 2/12 thine electronics, inc. THC63LVD103D _rev.3.0_e pin out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 lvds gnd lvds gnd lvds gnd te+ te- tclk+ tclk- td+ td- lvds vcc tc+ tc- tb+ tb- ta+ ta- 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 gnd gnd gnd gnd gnd ta0 ta1 ta2 ta3 ta4 ta5 ta6 tb5 tb4 tb3 tb2 tb1 tb0 rs vcc vcc tb6 tc1 tc2 tc3 tc3 tc4 tc4 tc4 tc5 tc6 td0 tc0 td2 td1 td3 td4 td5 td6 te0 te1 te2 te3 te4 te5 te6 r/f /pdwn pll gnd pll vcc clk in
copyright?2011 thine electronics, inc. 3/12 thine electronics, inc. THC63LVD103D _rev.3.0_e pin description pin name pin # type description ta+, ta- 30, 31 lvds out lvds data out. tb+, tb- 28, 29 lvds out tc+, tc- 24, 25 lvds out td+, td- 20, 21 lvds out te+,te- 18, 19 lvds out tclk+, tclk- 22, 23 lvds out lvds clock out. ta0 ~ ta6 33,34,35,36,37,38,40 in pixel data inputs. tb0 ~ tb6 41,42,44,45,46,48,49 in tc0 ~ tc6 50,52,53,54,55,57,58 in td0 ~ td6 59,61,62,63,64,1,3 in te0 ~ te6 4,5,6,8,9,11,16 in /pdwn 13 in h: normal operation, l: power down (all outputs are hi-z) rs 43 in lvds swing mode, vref select.see fig4, 5. r/f 60 in input clock triggering edge select. h: rising edge, l: falling edge vcc 51, 7 power power supply pins for ttl inputs and digital circuitry. clkin 12 in clock in. gnd 2, 10, 39, 47, 56 ground ground pins for ttl inputs and digital circuitry. lvds vcc 27 power power supply pins for lvds outputs. lvds gnd 17, 26, 32 ground ground pins for lvds outputs. pll vcc 15 power power supply pin for pll circuitry. pll gnd 14 ground ground pins for pll circuitry. rs lvds swing small swing input support vcc 350mv n/a 0.6 ~ 1.4v 350mv rs=vref a a. vref is input reference voltage. gnd 200mv n/a
copyright?2011 thine electronics, inc. 4/12 thine electronics, inc. THC63LVD103D _rev.3.0_e absolute maximum ratings 1 supply voltage (v cc ) -0.3v ~ +4.0v cmos/ttl input voltage -0.3v ~ (v cc + 0.3v) cmos/ttl output voltage -0.3v ~ (v cc + 0.3v) lvds transmitter output voltage -0.3v ~ (v cc + 0.3v) junction temperature +125 storage temperature range -55 ~ +150 reflow peak temperature / time +260 / 10sec. maximum power dissipation @+25 2.1w 1. ?absolute maximum ratings? are those valued beyond which the safety of the device can not be guaranteed. they are not meant to imply that the device should be operated at th ese limits. the tables of ?electrical charac- teristics? specify condit ions for device operation. c c c c c
copyright?2011 thine electronics, inc. 5/12 thine electronics, inc. THC63LVD103D _rev.3.0_e electrical characteristics cmos/ttl dc specifications v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 notes: 1 v ddq voltage defines max voltage of small swing input. it is not an actual input voltage. 2 small swing signal is applied to ta[6:0], tb[6:0], tc[6:0], td[6:0 ], te[6:0] and clkin. lvds transmitter dc specifications v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 symbol parameter conditions min. typ. max. units v ih high level input voltage rs=vcc or gnd 2.0 v cc v v il low level input voltage rs=vcc or gnd gnd 0.8 v v ddq 1 small swing voltage 1.2 2.8 v v ref input reference voltage small swing (rs=v ddq /2) v ddq /2 v sh 2 small swing high level input voltage v ref = v ddq /2 v ddq /2 +100mv v v sl 2 small swing low level input voltage v ref = v ddq /2 v ddq /2 -100mv v i inc input current a symbol parameter conditions min. typ. max. units vod differential output voltage rl=100 normal swing rs=vcc 250 350 450 mv reduced swing rs=gnd 100 200 300 mv vod change in vod between complementary output states rl=100 35 mv voc common mode voltage 1.125 1.25 1.375 v voc change in voc between complementary output states 35 mv i os output short circuit current vout=0v, rl=100 -24 ma i oz output tri-state current /pdwn=0v, v out =0v to vcc a c c 0v v in v cc ? 10 c c 10
copyright?2011 thine electronics, inc. 6/12 thine electronics, inc. THC63LVD103D _rev.3.0_e supply current v cc = 3.0v ~ 3.6v, ta =0 ~ +70 . symbol parameter conditions typ. max. units i tccw transmitter supply current rl=100 ,cl=5pf v cc =3.3v, rs=v cc worst case pattern f=85mhz 69 75 ma f=135mhz 87 93 ma f=160mhz 97 104 ma rl=100 ,cl=5pf v cc =3.3v, rs=gnd worst case pattern f=85mhz 55 61 ma f=135mhz 73 79 ma f=160mhz 83 89 ma i tccs transmitter power down supply current /pdwn = l, all inputs = l or h 10 a c c clkin tx0 worst case pattern tx1 tx2 tx3 tx4 tx5 tx6 x=a,b,c,d,e fig1. worst case pattern
copyright?2011 thine electronics, inc. 7/12 thine electronics, inc. THC63LVD103D _rev.3.0_e switching characteristics v cc = 3.0v ~ 3.6v, ta = 0 ~ +70 symbol parameter min. typ. max. units t tcit clk in transition time 5.0 ns t tcp clk in period 6.25 125.0 ns t tch clk in high time 0.35t tcp 0.5t tcp 0.65t tcp ns t tcl clk in low time 0.35t tcp 0.5t tcp 0.65t tcp ns t tcd clk in to tclk+/- delay 3t tcp ns t ts ttl data setup to clk in 2.0 ns t th ttl data hold from ckl in 0.0 ns t lvt lvds transition time 0.6 1.5 ns t top1 output data position0 (t tcp =6.25ns~20ns) -0.15 0.0 +0.15 ns t top0 output data position1 (t tcp =6.25ns~20ns) ns t top6 output data position2 (t tcp =6.25ns~20ns) ns t top5 output data position3 (t tcp =6.25ns~20ns) ns t top4 output data position4 (t tcp =6.25ns~20ns) ns t top3 output data position5 (t tcp =6.25ns~20ns) ns t top2 output data position6 (t tcp =6.25ns~20ns) ns t tpll phase lock loop set 10.0 ms c c t tcp 7 ----------- 0 . 1 5 ? t tcp 7 ----------- t tcp 7 ----------- 0 . 1 5 + 2 t tcp 7 ----------- 0 . 1 5 ? 2 t tcp 7 ----------- 2 t tcp 7 ----------- 0 . 1 5 + 3 t tcp 7 ----------- 0 . 1 5 ? 3 t tcp 7 ----------- 3 t tcp 7 ----------- 0 . 1 5 + 4 t tcp 7 ----------- 0 . 1 5 ? 4 t tcp 7 ----------- 4 t tcp 7 ----------- 0 . 1 5 + 5 t tcp 7 ----------- 0 . 1 5 ? 5 t tcp 7 ----------- 5 t tcp 7 ----------- 0 . 1 5 + 6 t tcp 7 ----------- 0 . 1 5 ? 6 t tcp 7 ----------- 6 t tcp 7 ----------- 0 . 1 5 + ac timing diagrams 5pf 20% 80% 20% 80% t lvt t lvt clk in lvds output 90% 10% 90% 10% t tcit t tcit v diff 100 v diff =(ta+)-(ta-) ta+ ta- lvds output load fig2. clkin transition time fig3. lvds output load and transition time ttl input
copyright?2011 thine electronics, inc. 8/12 thine electronics, inc. THC63LVD103D _rev.3.0_e ac timing diagrams ttl inputs t tcp t ts t th t tch t tcl clk in tx0-tx6 t tcd note: clk in: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. tclk+ tclk- small swing inputs t tcp t ts t th t tch t tcl clk in tx0-tx6 t tcd note: clk in: for r/f=gnd, denote as solid line, for r/f=vcc, denote as dashed line. tclk+ tclk- v ddq gnd gnd v ddq v ref voc voc v ref vcc/2 vcc/2 vcc/2 vcc/2 v ddq /2 v ddq /2 v ddq /2 v ddq /2 v ddq /2 vcc/2 fig4. clkin period, high/low time, setup/hold timing fig5. small swing inputs gnd vcc gnd vcc vod rs pin vod vcc 350mv 0.6~1.4v gnd 200mv rs pin vref vcc vcc/2 0.6~1.4v input voltage of rs pin gnd vcc/2
copyright?2011 thine electronics, inc. 9/12 thine electronics, inc. THC63LVD103D _rev.3.0_e ac timing diagrams phase lock loop set time v diff = 0v v diff = 0v tclk+/- t top1 t top0 t top6 t top5 t top4 t top3 t top2 lvds output te6 te5 te4 te3 te2 te1 te0 te+/- td6 td5 td4 td3 td2 td1 td0 td+/- tc6 tc5 tc4 tc3 tc2 tc1 tc0 tc+/- tb6 tb5 tb4 tb3 tb2 tb1 tb0 tb+/- ta6 ta5 ta4 ta3 ta2 ta1 ta0 ta+/- (differential) next cycle previous cycle fig6. lvds output data position 2.0v clkin /pdwn tclk+/- 3.0v 3.6v vcc t tpll v diff = 0v fig7. pll lock set time
THC63LVD103D _rev.3.0_e copyright?2011 thine electronics, inc. 10/12 thine electronics, inc. note 1)cable connection and disconnection don't connect and disconnec t the lvds cable, when the powe r is supplied to the system. 2)gnd connection connect the each gnd of the pcb which THC63LVD103D a nd lvds-rx on it. it is better for emi reduction to place gnd cable as close to lvds cable as possible. 3)multi drop connection multi drop connection is not recommended. 4)asynchronous use asynchronous use such as following systems are not recommended. lvds-rx THC63LVD103D lvds-rx tclk+ tclk- THC63LVD103D THC63LVD103D ic clkout clkout data data lvds-rx lvds-rx ic tclk+ tclk- tclk+ tclk- clkout data data THC63LVD103D THC63LVD103D ic tclk+ tclk- tclk+ tclk- clkout clkout data data ic
copyright?2011 thine electronics, inc. 11/12 thine electronics, inc. THC63LVD103D _rev.3.0_e package s seating plane 0.08 m 0.10 1.00 ref. 0.60+/-0.15 0.25mm gage plane 0.20+/-0.03 1.00+/-0.05 0.05~0.15 1.2 max 0.50 bsc. 0.09~0.20 s 3.5+/-3.5 degree 10.00 bsc. 10.00 bsc. 12.00 bsc. 12.00 bsc. unit : mm THC63LVD103D
THC63LVD103D _rev.3.0_e copyright?2011 thine electronics, inc. 12/12 thine electronics, inc. notices and requests 1. the product specifications describe d in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer's design. we are not responsible for possible errors and omissions in this material. please note if erro rs or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copy right, know-how or other proprietary. copying or disclosing to third parties the contents of this material without our prior pe rmission is prohibited. 4. note that if infringement of any third party's industrial owne rship should occur by using this product, we will be exempted fro m the responsibility unless it dire ctly relates to the production process or functions of the product. 5. this product is presumed to be used for general electric equi pment, not for the applications which require very high reliability (i ncluding medical equipment directly concerning people's life, aerospace equipment, or nuclear control equipm ent). also, when using this product for the equipment concerned with the cont rol and safety of th e transportation means, the traffic signal equipment, or various types of safety equipmen t, please do it after appl ying appropriate measures to the product. 6. despite our utmost efforts to imp rove the quality and reliability of the product, faults will occur with a certain small probability, wh ich is inevitable to a semi-cond uctor product. therefore, you are encouraged to have sufficien tly redundant or error preventive design applied to the use of the product so as not to have our produc t cause any social or public damage. 7. please note that this product is not designed to be radiation-proof. 8. customers are asked, if required, to judge by themselves if th is product falls under the category of strategic goods under the foreign exchange and foreign trade control law. thine electronics, inc. e-mail: sales@thine.co.jp

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